The present invention relates to a semiconductor integrated circuit device in which a volatile memory, such as a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory), and an electrically rewritable or reprogrammable nonvolatile memory, such as a flash memory, are packaged together with a control processing unit, such as a central processing unit, over a semiconductor substrate; and, more particularly, the invention relates to a repair technique which is effective when applied to an on-chip type large-scale integrated circuit, such as a DRAM-consolidated LSI (Large-Scale Integration), a DRAM-embedded LSI of a system LSI.
Nowadays, the large scale of a semiconductor integrated circuit device is in the category of a system on-chip, such as a DRAM-consolidated LSI, a DRAM-embedded LSI or a system LSI.
As a semiconductor integrated circuit device is provided with a larger scale, its internal defects can be less ignored. Especially, a memory, such as a DRAM, a SRAM or a flash memory, is expected to have a relatively small area, but a large storage capacity, so that it becomes susceptible to defects caused by the remarkably fine working during manufacture and the resultant miniaturization of signals. Therefore, the application of a redundancy circuit technique to such semiconductor circuit devices is important so that an expected system operation can be achieved irrespective of the occurrence of more or less defects.
For enlarging the scale of a semiconductor integrated circuit device, it is frequently desirable to apply a trimming technique for achieving the desired circuit characteristics. By this trimming technique, an analog amount, such as an internal voltage or current, and a quasi-analog amount, such as the timing of a timing signal, can be sufficiently brought to a desired value irrespective of the manufacturing dispersion of the semiconductor integrated circuit device.
The redundancy circuit technique and the trimming technique for a large-scale semiconductor integrated circuit device are well-known. One such technique is disclosed in Japanese Patent Laid-Open No. 334999/1995, and in corresponding U.S. Pat. No. 5,561,627, of Hitachi, Ltd., and is used in a program for providing defect repair information using the memory cells of an electrically reprogrammable nonvolatile memory, such as a flash memory. In this technique, repair information specifying a defective memory cell in the nonvolatile memory is stored in the memory cell of the nonvolatile memory; the repair information is latched in an internal latch circuit at the time of initialization; and the latched repair information and an access address are compared so that the access is replaced, in the case of coincidence, by the access to a redundant memory cell.
On the other hand, another technique is disclosed in Japanese Patent Laid-Open No. 214496/1998, and in corresponding U.S. patent application Ser. No. 09/016,300, of Hitachi, Ltd., and in which trimming information is stored for use in the storage region of a portion of a nonvolatile memory, such as a flash memory. In accordance with this technique, more specifically, there is provided a trimming circuit for finely adjusting the output clamp voltage of voltage clamp means for providing an operating power source for the flash memory so that the trimming information for determining the state of the timing circuit is programmed in the memory cells of the flash memory. The programmed trimming information is read out in a reset operation from the flash memory and is internally transferred to a register. The state of the trimming circuit is determined by using the transferred trimming information. As a result, the clamp voltage to be outputted from voltage clamp means is trimmed to a value suitable for the operation of the flash memory, thereby compensating for the manufacturing dispersion of the semiconductor integrated circuit device.
An example of a system LSI is described on pp. 34 to 38 of xe2x80x9cElectronic Materialsxe2x80x9d (issued in January, 1998, by Kabushiki Gaisha Kogyo Chosakai), wherein, as seen in FIG. 4 thereof, a volatile memory, such as a flash memory, and a DRAM are consolidated together with a CPU (Central Processing Unit). The technique for forming the nonvolatile memory and the DRAM by a common process is already described in U.S. Pat. No. 5,057,448. On the other hand, examples of a semiconductor integrated circuit device packaging a flash memory and a DRAM together with a CPU on one semiconductor substrate are described in Japanese Patent Laid-Open Nos. 52293/1989 and 124381/1998.
Our preceding patent application has proposed the use of storage elements of one flash memory for repairing a defect or to effect trimming within a closed range of the flash memory. In view of the large-scale integration represented by a system on-chip, we have investigated the efficient use of a nonvolatile memory, or one circuit module packaged in the large-scale integrated circuit device in relation to another circuit module. In the course of this investigation, we have considered the utilization of the stored information of the nonvolatile memory to repair a defect of a volatile memory, other than the nonvolatile memory itself we have recognized the following new problems in the investigation of such repair of a volatile memory.
In order to provide the nonvolatile memory with the required repair information, more specifically, a procedure is needed to reflect the repair information on the volatile memory. This reflection of the information desirably should be realized at a high speed, even if the amount of repair information increases, to cope with an increase in the defects in accordance with the construction of the volatile memory or the provision of a large storage capacity.
In studies subsequent to that investigation, Japanese Patent Laid-Open No. 131897/1994 has been found, in which it is proposed to use a programmable ROM for repairing a defect in the cache memory. However, the programmable ROM in this case is a dedicated circuit element belonging to a redundancy memory control circuit in the cache memory, but represents no more than a repairing technique in the closed range of the cache memory, and has failed to adequately address our aforementioned problems, even if it is resultantly compared.
An object of the present invention is to provide a semiconductor integrated circuit device which is capable of improving the changing efficiency of a coupling change, such as a defect repair, in a circuit having a large scale logic construction, in which a nonvolatile memory made accessible by a control processing device and a volatile memory are packaged.
Moreover, an object of the present invention is to realize a cost by improving the yield of a semiconductor integrated circuit device which has been strictly demanded to have a lower cost because of its large-scale logic.
Another object of the present invention is to improve the usability of a memory module by consolidating the specifications of the defect repair of the memory module in a semiconductor integrated circuit device having a volatile memory, such as a DRAM or a SRAM, as the memory module.
Still another object of the present invention is to provide a data storage device in which there is stored design data to be used for designing a semiconductor integrated circuit device by using a computer.
The foregoing and other objects and novel features of the invention will become more apparent from the following description when taken with reference to the accompanying drawings.
Representative aspects of the invention to be described herein will be briefly summarized in the following.
A first semiconductor integrated circuit device (1A, 1C) according to the invention comprises, over one semiconductor substrate: an electrically reprogrammable nonvolatile memory (11) capable of being accessed by a control processing device (10), such as a central processing unit; and a volatile memory (12, 13) capable of being accessed by the control processing device, so that the stored information of the nonvolatile memory may be utilized for a connection change to effect a defect repair of the volatile memory. Specifically, the volatile memory includes: a plurality of first volatile memory cells, such as normal volatile memory cells, and a plurality of second volatile memory cells, such as redundancy volatile memory cells; and a volatile storage circuit (12AR, 13AR) for holding coupling control information for enabling the first volatile memory cells to be replaced by the second volatile memory cells. The nonvolatile memory includes a plurality of nonvolatile memory cells, some of which are used for storing coupling control information, so that the coupling control information is read out from the nonvolatile memory cells and outputted by the reading and setting operations of the coupling control information, such as an instruction to initialize the semiconductor integrated circuit device. The volatile storage circuit is caused to fetch and store the coupling control information from the nonvolatile memory by the reading and setting operations.
A second semiconductor integrated circuit device (1B) according to the invention additionally utilizes the stored information of a nonvolatile memory for repairing a defect of the nonvolatile memory. Specifically, the volatile memory includes: a plurality of normal volatile memory cells and a plurality of redundancy volatile memory cells; and a volatile storage circuit (12AR, 13AR) for holding the repair information for repairing a defective normal volatile memory cell by replacing it with one of the redundancy volatile memory cells. The non-volatile memory includes: a plurality of normal nonvolatile memory cells and a plurality of redundancy nonvolatile memory cells; and a volatile storage circuit (11AR) for holding the repair information for repairing a defective normal nonvolatile memory cell by replacing it with one of the redundancy nonvolatile memory cells. Some of the nonvolatile memory cells are memory cells for storing the information needed for repair of the volatile memory and the information needed for repair of the nonvolatile memory. The repair information, as stored in some nonvolatile memory cells, is read out from the nonvolatile memory cells by executing reading and setting operations, such as an operation to initialize the semiconductor integrated circuit device, and is fed to and held in the volatile storage circuit in the volatile memory and the volatile storage circuit in the nonvolatile memory.
According to the first and second semiconductor integrated circuit devices, the information for coupling control, such as defect repair, is programmed in the nonvolatile memory in place of elements, such as the fuse elements, so that the fuse program circuit, the might otherwise be needed for using the fuse elements, can be eliminated. Accordingly, the use or step in the manufacture of an apparatus, which is liable to have a relatively high price, such as a laser cutting apparatus for cutting a fuse, can be eliminated to lower the cost of manufacture. When the fuse elements are provided, they need to be positioned at a relatively high layer portion over the semiconductor substrate so that they can be cut even in the presence of a layer which makes the fuse cutting difficult, such as an aluminum wiring layer to be used for wiring the semiconductor integrated circuit device or a copper wiring provided to make the signal propagation delay time shorter. For this structural reason and for avoiding thermal damage to an insulating film or surface protecting film covering the semiconductor substrate surface by a laser beam used to cut the fuse, an opening for the laser exposure has to be formed in the insulating film or the surface protecting film over the fuse elements. Because such a complicated manufacturing process is required, the semiconductor integrated circuit device itself has a high price. In addition, when the fuse elements are provided, their size reduction is restricted by the need to provide openings for the laser exposure, so that the semiconductor substrate takes on a relatively large size. If the fuse program circuit is not used, the manufacturing process is simplified. When a nonvolatile memory is utilized for storing the coupling control information, it is possible to enjoy an advantage in the information can be reprogrammed at an arbitrary time and several times. This makes it possible to sufficiently cope with the coupling change for a defect which occurs at a relatively later step in the manufacturing process, such as the burn-in step in the manufacture of the semiconductor integrated circuit device, or a coupling change for a defect which occurs after the packaging over the system or the circuit substrate has aged. As a result, a circuit having a large-scale logic construction, in which a volatile memory is packaged together with a nonvolatile memory, can be sufficiently utilized because it can be changed after manufacture. Therefore, a cost reduction can be realized by improving the yield of the semiconductor integrated circuit device having large-scale logic.
The data input terminals of the individual volatile storage circuits (11AR, 12AR, 13AR) are coupled to a data bus (16) with which the individual data input/output terminals of the nonvolatile memory and the volatile memory are commonly connected, so that the coupling control information outputted from the nonvolatile memory can be transmitted through the data bus to the corresponding volatile storage circuit by the operations to read out and set the coupling control information, such as the initialization produced by the control processing device, such as the central processing unit. As a result, the general-purpose utility of the nonvolatile memory can be warranted with respect to access to the nonvolatile memory by the control processing device.
If there is adopted a construction in which the volatile storage circuit in the volatile memory is connected with the data bus, no consideration need be given to the addition of special wiring lines for transmitting the coupling control information, such as the repair information, even when the number of volatile memories is increased.
If the bit number of the entire coupling control information is less than that of the data bus, the coupling control information may be programmed in parallel in all the volatile storage circuits by connecting the signals lines of the data bus separately with the data input terminals of the individual volatile storage circuits.
When the scale of the semiconductor integrated circuit device is large, the frequency of coupling changes against defects is accordingly increased to raise the probability of increasing the coupling control information. When the data bus width, i.e., the bit number of the data bus is small for the increased coupling control information, the individual volatile storage circuits can be programmed in series with the coupling control information. In this case, when the coupling control information is consecutively read out in a plurality of divided cycles from the nonvolatile memory cells and outputted to the data bus in response to a setting operation instruction, such as an instruction to initialize the semiconductor integrated circuit device, the coupling control information to be fed for each reading cycle through the data bus may be consecutively fetched and held for each of the reading cycles by the volatile storage circuit.
Especially in view of the large-scale integration represented by the system on-chip, the following items will become apparent. More specifically, in order that the nonvolatile memory, or one circuit module or memory module packaged on the large-scale integrated circuit device, may be efficiently utilized in relation to another circuit module or memory module, the stored information of the nonvolatile memory is utilized for coupling control, such as a defect repair of a volatile memory other than the nonvolatile memory. In this case, the means for effecting transfer of the coupling control information through the data bus and the series internal transfer of the plurality of cycles of the coupling control information is excellent in that, when the information or an objective of the coupling control, such as a defect, increases with an increase in the capacity of the volatile memory, the process to reflect the control information on the individual volatile memories in accordance with an increase in the amount of control information can be realized at a high speed.
In order to program the volatile storage circuit with the coupling control information using a simple construction, the volatile storage circuit may hold the coupling control information outputted from the nonvolatile memory, in response to a first state indicating the reset period of a reset signal (RESET) instructing the initialization of the semiconductor integrated circuit device, and the control processing device may start a reset exceptional operation in response to the change of the reset signal from the first state to a second state indicating the release or end of reset. In this case, the reset signal has to be kept in the first state for the period necessary for programming the coupling control information. In other words, the reset release timing by the reset signal should not be premature.
In order to provide a sufficient time for programming of the coupling control information without any substantial restriction on the reset release timing of the reset signal, there can be provided a clock control circuit (19, 20) which is initialized in response to the first state (or reset period) of the reset signal (RESET) instructing the initialization of the semiconductor integrated circuit device. In response to the change of the reset signal from the first state to the second state, the clock control circuit causes the volatile storage circuit to fetch and hold the coupling control information from the nonvolatile memory, and then the central processing unit is allowed to start the reset exceptional operation.
Since the nonvolatile memory is reprogrammable, the coupling control information programmed in advance may accordingly be erroneously programmed. In order to exclude this disadvantage as much as possible, it is advisable to allow the nonvolatile memory to be set by a mode bit (MB2) to an operation mode to allow the reprogramming of the nonvolatile memory cells for storing the repair information and to an operation mode to inhibit the reprogramming.
On the other hand, it is also possible to set by a mode bit (MB1) an operation mode to allow the reprogramming of the nonvolatile memory cells by a write device connected to the outside of the semiconductor integrated circuit device, and an operation mode to allow the reprogramming of the nonvolatile memory cells in accordance with the execution of an instruction by the central processing unit. Then, the coupling control information can be programmed either on a packaged board (or on-board) or by the write device. In order to easily realize the coupling change corresponding to a defect which will occur after the packaging of the semiconductor integrated circuit device, it is desired to support the on-board programming mode.
In order to update the coupling control information, such as a demand for repairing a defect due to the on-board programming, the nonvolatile memory may store a diagnostic program. The diagnostic program causes the central processing unit to execute operations to detect a defect against the nonvolatile memory and the volatile memory and to program the repair information storing nonvolatile memory cells of the nonvolatile memory with the repair information for repairing a newly defective memory cell.
A third semiconductor integrated circuit device (30) according to the present invention extends the information, as stored for use in the nonvolatile memory (11), to one other than the information used for the repair of a defect. Specifically, the semiconductor integrated circuit device (30) comprises, over one semiconductor substrate, while sharing a data bus (16): a control processing device, such as a central processing unit (10); an electrically reprogrammable nonvolatile memory (11) which is able to be accessed by the control processing device; and a volatile memory (12, 13) which is able to be accessed by the control processing device. The nonvolatile memory and the volatile memory individually include register means (11AR, 12AR, 13AR, AR, 31DR, 12DR, 13DR) having data input terminals connected with the data bus, so that their individual functions are partially determined according to the function control information set by the individually corresponding register means. The nonvolatile memory includes a plurality of nonvolatile memory cells, some of which are used for storing initialization data containing the function control information. On the other hand, the nonvolatile memory has an operation mode to allow the reprogramming of the nonvolatile memory cells for storing initialization data and an operation mode to inhibit the reprogramming, so that the initialization data are read out from the nonvolatile memory cells and outputted in response to an instruction to initialize the semiconductor integrated circuit device. In response to the instruction to initialize the semiconductor integrated circuit device, the register means fetches and holds the initialization data from the nonvolatile memory.
In this third semiconductor integrated circuit device, in order to load each register means reliably with a large amount of initialization data in response to a reset instruction, there may be provided a clock control circuit which is initialized in response to the first state of the reset signal for instructing the initialization of the semiconductor integrated circuit device. In response to the state change of the reset signal from the first state to the second state, for example, this clock control circuit outputs a first timing signal having a plurality of phases shifted in activation timing from one another, and then outputs a second timing signal for causing the control processing device to start the reset exceptional operation. In response to the activation timing of the first timing signal having a plurality of phases, the nonvolatile memory reads the initialization data consecutively in a plurality of divided cycles from the nonvolatile memory cells and outputs them to the data bus. The register means performs an input setting operation to fetch and hold the data of the data bus consecutively for all reading cycles of the initialization data from the nonvolatile memory.
The nonvolatile memory can utilize the information held by a corresponding one of the register means, as repair information for repairing defective normal nonvolatile memory cells by replacing them with redundancy nonvolatile memory cells.
The volatile memory can utilize the information held by the corresponding one of the register means, as repair information for repairing the defective normal volatile memory cells by replacing them with redundancy volatile memory cells.
The volatile memory may be constructed to include dynamic memory cells as the volatile memory cells and to utilize the information held by the register means corresponding to the volatile memory, as the control information for specifying the refresh interval of the dynamic memory cells.
The volatile memory may also be constructed to utilize the information held by the corresponding one of the register means, as control information for specifying the timing of an internal control signal.
In this third semiconductor integrated circuit device, like before, it is also possible to efficiently change the coupling of a circuit which has a large-scale logic construction having a volatile memory packaged together with a nonvolatile memory. As a result, the yield of the semiconductor integrated circuit device having the large-scale logic can be improved to realize a cost-reduction.
The nonvolatile memory is exemplified by a flash memory, and some of nonvolatile memory cells are able to store a program to be executed by the control processing device. The volatile memory is exemplified by a DRAM and can be utilized as a work memory of the control processing device. The volatile memory can be exemplified by a fast access memory in the form of a SRAM.
In a semiconductor integrated circuit device (1A, 1B, 1C) including a volatile memory (12, 13), such as a DRAM or a SRAM, as the memory module, the memory module includes a volatile storage circuit (12AR, 13AR) for storing repair information on the memory array in a volatile state. The volatile storage circuit (12AR, 13AR) includes: a plurality of input terminals or input nodes which can be coupled to the data base to be formed in the semiconductor integrated circuit device; and a control signal input terminal for receiving a control signal (reset) for an operation to set the reading of the repair information, such as an operation to initialize the semiconductor integrated circuit device. The memory module includes a plurality of first volatile memory cells, such as normal volatile memory cells, and a plurality of second volatile memory cells, such as redundancy volatile memory cells, and the volatile storage circuit (12AR, 13AR) operates to hold repair information for enabling the first volatile memory cells to-be replaced by the second volatile memory cells.
The construction is such that the repair information to be set in the volatile storage circuit (12AR, 13AR) is fed from the outside of the memory module to the volatile storage circuit (12AR, 13AR) in the memory module, and the specifications of the circuit or function relating to defect repair of the memory module packaged in the semiconductor integrated circuit device are standardized or unified. As a result, the usability of the memory module can be improved when it is sold as memory module part, i.e., an IP (Intellectual Property) part.
The semiconductor integrated circuit device including a memory module is designed by a designing machine composed of a computer (or electronic computer), the design data such as the layout data for determining the construction of the volatile storage circuit (12AR, 13AR), the circuit function data or the connection data are described in such specific computer languages as can be understood by the computer. Moreover, the data is serviced as a storage device, such as the magnetic tape, a MO (Magneto-Optical disk), a CD-ROM or a floppy disk. On the other hand, the design data of the volatile storage circuit (12AR, 13AR) may be serviced while being stored in the data storage device together with the design data of the circuit functions of the memory module of the volatile memory, such as a DRAM or a SRAM. Still moreover, the design data of the volatile storage circuit (12AR, 13AR) may be stored in the data storage device while being assembled in the design data of the memory module of the volatile memory, such as a DRAM or a SRAM.
By thus storing and servicing the design data of the memory module and the semiconductor integrated circuit device containing the former as design data, as described in specific computer languages can be understood by the computer, in the storage device, it is possible to efficiently design the memory module or the semiconductor integrated circuit device containing the former.
FIG. 1 is a block diagram showing a first single chip microcomputer representing one example of the semiconductor integrated circuit device of the invention;
FIG. 2 is a diagram showing one detailed example of the repair information to be used by the single chip microcomputer of FIG. 1;
FIG. 3 is a timing chart showing one example of an initial programming operation of the repair information for a reset period;
FIGS. 4(A) and 4(B) are flow charts showing a defect repairable timing for the single chip microcomputer in time series from a manufacturing step;
FIG. 5 is a device cross section schematically showing the behavior of a laser-fusing opening of a fuse for a copper wiring process;
FIG. 6 is a circuit diagram showing one example of a dynamic memory cell;
FIG. 7 is a schematic diagram showing one example of a memory cell array of a DRAM;
FIG. 8 is a circuit diagram showing one example of a CMOS static memory cell;
FIG. 9 is a schematic diagram showing one example of a memory cell array of a SRAM;
FIG. 10 is a circuit diagram showing one example of a flash memory cell;
FIG. 11 is a schematic diagram showing one example of a memory cell array of a flash memory;
FIG. 12 is a characteristic diagram showing one example of a programming state and an erase state in the flash memory;
FIG. 13 is a diagram showing one example of the voltage applied states in the programming operation and the erase operation of the flash memory;
FIG. 14 is a block diagram of a second single chip microcomputer another embodiment of the semiconductor integrated circuit device according to the invention;
FIG. 15 is a diagram showing one example of the repair information in the second single chip microcomputer;
FIG. 16 is a timing chart showing one example of an initial programming operation of the repair information in the second single chip microcomputer;
FIG. 17 is a block diagram showing a third single chip microcomputer representing still another embodiment of the semiconductor integrated circuit device according to the invention;
FIG. 18 is a timing chart showing one example of a process for initial programming of a reset period with the repair information in the third single chip microcomputer;
FIG. 19 is a block diagram schematically showing one example of a memory adopting a construction in which the defect repair is performed by replacing a memory mat or a memory block;
FIG. 20 is a block diagram showing one example of a single chip microcomputer having a voltage step-down circuit;
FIG. 21 is a circuit diagram showing one example of the voltage step-down circuit;
FIG. 22 is a circuit diagram showing one example of a refresh timer for controlling the refresh interval of a memory cell in a data holding mode of a DRAM 12;
FIG. 23 is a timing chart showing one example of the operations of the refresh timer exemplified in FIG. 23;
FIG. 24 is a circuit diagram showing one example of a timing adjustment circuit of a sense amplifier activation signal in a timing controller of a SRAM 13;
FIG. 25 is a diagram showing one example of a format of the initialization data which are stored in the flash memory when the techniques individually explained in the defect repair of FIG. 14, the voltage trimming of FIG. 21, the refresh interval optimization of FIG. 22 and the timing adjustment of the timing controller of FIG. 24 are applied in, connection with one single chip microcomputer exemplified in FIG. 20; and
FIG. 26 is a conceptional diagram showing one example of a system for designing a semiconductor integrated circuit device according to the invention by using a computer.